Bottom electrode of capacitor of semiconductor device and method of forming the same

ABSTRACT

To form a bottom electrode of a capacitor of a semiconductor device, a first insulation layer pattern having a first contact hole is formed on a substrate, and a contact plug for the bottom electrode is formed in the contact hole. A second insulation layer is formed on the first insulation layer pattern and the contact plug. The second insulation layer has a second etching rate higher than a first etching rate of the first insulation layer pattern. The second insulation layer is etched to form a second insulation layer pattern having a second a contact hole exposing the contact plug. A conductive film is formed on the sidewall and the bottom face of the second contact hole. According to the difference between the first etching rate and the second etching rate, the etching of the first insulation layer pattern near the contact plug is reduced.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. patent Ser. No. 10/670,485,filed on Sep. 24, 2003, now pending, which claims priority from KoreanPatent Application No. 2003-533, filed on Jan. 6, 2003, which are herebyincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This disclosure relates to a bottom electrode of a capacitor of asemiconductor device and a method of forming the same, and moreparticularly to a bottom electrode of a cylindrical shaped capacitor anda method of forming the same.

2. Description of the Related Art

As computers have been widely used in recent years, demands forsemiconductor devices have been increased. Accordingly, semiconductordevices with high response speeds and high storage capacities arerequired. To meet these needs, semiconductor device fabricationtechniques have been developed that improve integration density,response speeds, and reliability.

For example, a semiconductor device like a dynamic random access memory(DRAM) device has large storage capacity while information data isfreely inputted and/or outputted into and/or from the DRAM device. TheDRAM device generally includes a memory cell that stores the informationdata as the form of charges, and a peripheral circuit area that controlsthe information data. The memory cell of the DRAM device usuallyincludes one access transistor and one accumulation capacitor.

To achieve highly integrated DRAM devices, various researches have beenmade on the formation of a capacitor in a minute memory cell thereof sothat the DRAM device has sufficient storage capacity. The capacitor maybe formed using several methods that ensure sufficient storage capacity.Usually, they involve using a high permittivity material as a dielectriclayer or increasing the effective area of the capacitor by employing ahemisphere silicon grain (HSG) growth process.

However, the HSG growth process demands complicated and costly steps,decreasing the productivity of the DRAM devices. Additionally, when ahigh permittivity material is used as a dielectric layer, theproductivity of the DRAM device may also decrease due to processvariations when the capacitor is formed.

Accordingly, a method of increasing the height of the capacitor and amethod of varying the shape of the capacitor have been developed toobtain sufficient storage capacity of the DRAM device. In these methods,the height and shape of the capacitor are varied while the horizontalsize of the capacitor is maintained. For example, a bottom electrodewith a fin shape or a cylindrical shape may be provided.

The height of the capacitor is more than about 15,000 Å for a recentGiga-graded DRAM device. Thus, a cylindrical shaped capacitor having aheight of more than 15,000 Å is employed to ensure the sufficientstorage capacity of the DRAM device.

U.S. Pat. No. 6,228,736 (issued to Lee et. al.) and U.S. Pat. No.6,080,620 (issued to Jeng) disclose cylindrical shaped capacitors.Generally, when the height of the capacitor increases, the bottomelectrode of the capacitor may collapse during the capacitor fabricationprocess. In particular, the collapse of the bottom electrode frequentlyoccurs when the capacitor has a cylindrical shape because the capacitorexhibits an increasingly unstable structure as the height increases.

Japanese Patent Laid-Open Publication No. 13-57413 discloses acylindrical shaped capacitor having an improved bottom electrodestructure.

FIG. 1 is a schematic cross-sectional diagram illustrating a bottomelectrode of a conventional cylindrical shaped capacitor.

Referring to FIG. 1, the bottom electrode 10 of a cylindrical shapedcapacitor formed on a substrate 15 has a contact plug 11 formed throughan insulation layer pattern 17, and a node 13 connected to the contactplug 11. A pad (not shown) is positioned beneath the contact plug 11.

The node 13 of the bottom electrode 10 is divided into an upper node 13a and a lower node 13 b on the basis of their critical dimensions (CD).Here, the critical dimension (CD2) of the lower node 13 b is larger thanthe critical dimension (CD1) of the upper node 13 a. When the criticaldimension (CD2) of the lower node 13 b is larger than the criticaldimension (CD1) of the upper node 13 a, the cylindrical shaped capacitorstructure may be improved.

FIGS. 2A and 2B are cross-sectional diagrams illustrating a conventionalmethod of forming a bottom electrode of a cylindrical shaped capacitor.

Referring to FIG. 2A, after a first insulation layer is formed on asubstrate 20, the first insulation layer is patterned to form a firstinsulation layer pattern 22 having a first contact hole 23.

A conductive material is deposited on the first insulation layer pattern22 to fill up the first contact hole 23 so that a contact plug 24 forthe bottom electrode is formed in the first contact hole 23. Here, thecontact plug 24 is electrically connected to a pad (not shown) for thebottom electrode. In other words, the contact plug 24 is formed on thepad.

An etch stop layer 25, a second insulation layer 26 and a thirdinsulation layer 28 are sequentially formed on the first insulationlayer pattern 22 and on the contact plug 24. The second insulation layer26 is formed using a material with an etching rate different from thatof the third insulation layer 28.

Referring to FIG. 2B, the third insulation layer 28 is etched to form athird insulation layer pattern 28 a having a third contact hole 28 b.The portion of the second insulation layer 26 exposed through the thirdinsulation layer pattern 28 a is etched to form a second insulationlayer pattern 26 a having a second contact hole 26 b exposing thecontact plug 24. The third insulation layer pattern 28 a and the secondinsulation layer pattern 26 a are formed by in-situ processes. The etchstop layer 25 is etched when the second insulation layer pattern 26 a isformed.

The surface of the contact plug 24 is exposed when the second insulationlayer pattern 26 a and the third insulation layer pattern 28 a areformed. The critical dimension of the second contact hole 26 b of thesecond insulation layer pattern 26 a is larger than the criticaldimension of the third contact hole 28 b of the third insulation layerpattern 28 a because the etching rate of the second insulation layer 26is greater than that of the third insulation layer 28.

Unfortunately, part of the first insulation layer pattern 22 formed onan upper lateral portion (region A) of the contact plug 24 is etched aswell. In other words, the upper lateral portion (region A) of thecontact plug 24 is etched because the etching rate of the thirdinsulation layer 28 is different from that of the second insulationlayer 26. Also, the upper lateral portion (region A) of the contact plug24 is damaged when the third insulation layer 28 and the secondinsulation layer 26 are cleaned after the etching process.

During the etching and cleaning processes, the upper lateral portion ofthe contact plug may be damaged. More specially, an electrical bridgemay be generated between adjacent contact plugs when a conductive filmfor the bottom electrode is formed thereon. If a bridge is generatedbetween the contact plugs, the reliability of a semiconductor device,including the bottom electrode is seriously deteriorated. Embodiments ofthe invention address these and other disadvantages of the prior art.

SUMMARY OF THE INVENTION

Among other advantages, embodiments of the invention provide a bottomelectrode for a capacitor in a semiconductor device that includes aprotection layer pattern that prevents the formation of a bridge betweenadjacent contact plugs. Embodiments of the invention also provide abottom electrode having an enhanced cylindrical shape, thereby improvingthe electrical characteristics and increasing the stability of acapacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings.

FIG. 1 is a schematic cross-sectional diagram illustrating a bottomelectrode of a conventional cylindrical shaped capacitor.

FIGS. 2A and 2B are cross-sectional diagrams illustrating a conventionalmethod of forming the bottom electrode of a cylindrical shapedcapacitor.

FIGS. 3A to 3E are cross-sectional diagrams illustrating a method offorming the bottom electrode of a cylindrical shaped capacitor accordingto an embodiment of the invention.

FIG. 4 is an enlarged cross-sectional diagram illustrating the criticaldimension of the bottom electrode of a cylindrical shaped capacitorfabricated according to another embodiment of the invention.

FIGS. 5 and 6 are cross-sectional diagrams illustrating a method offorming the bottom electrode of a cylindrical shaped capacitor having aprotection layer pattern according to yet another embodiment of theinvention.

FIGS. 7A to 7D are cross-sectional diagrams illustrating a method offabricating a DRAM device according to still another embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

The invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likenumbers refer to like elements throughout. The relative thickness oflayers in the illustrations may be exaggerated for purposes ofdescribing the present invention.

FIGS. 3A to 3E are cross-sectional diagrams illustrating a method offorming a bottom electrode of a cylindrical shaped capacitor accordingto an embodiment of the present invention.

Referring to FIG. 3A, there is provided a substrate 30 having pads 31for bottom electrodes of capacitors. The pads 31 are formed in contactregions between gate electrodes (not shown). Each of the pads 31 servesas an electric channel between the bottom electrode of the capacitor andthe substrate 30.

A first insulation layer is formed on the substrate 30 having the pad 31formed thereon. For example, the first insulation layer is formed usingborophosphosilicate glass (BPSG). When the first insulation layercorresponds to a BPSG film, the first insulation layer has an etchingselectivity relative to a second insulation layer that is subsequentlyformed. The BPSG film is preferably about 3.5 to 4.5% by weight of boron(B) and about 3.3 to 3.7% by weight of phosphorous (P).

The first insulation layer on the substrate 30 is etched to form firstinsulation layer patterns 32 having first contact holes 33 exposing thepads 31. The first insulation layer patterns 32 are formed by aphotolithography process.

When the first insulation layer patterns 32 are formed, contaminantparticles are generated. The contaminants may remain on the firstinsulation layer patterns 32 after forming the first insulation layerpatterns 32. If the contaminants remain on the first insulation layerpatterns 32, a failure of the semiconductor device may result duringsubsequent processes.

Accordingly, a cleaning process is advantageously performed after thefirst contact holes 33 are formed. The cleaning process includes a wetcleaning process using a standard cleaning 1 (SC-1) solution or ahydrogen fluoride (HF) solution. In this case, the SC-1 solutionincludes ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂) anddeionized water (H₂O) by a volume ratio of about 1:1:5. Though the twosolutions can be used independently, it is preferable to sequentiallyuse the HF solution and then the SC-1 solution during the cleaningprocess. In the cleaning process, the substrate 30 is cleaned using theHF solution for about 100 seconds, and the substrate 30 is thensuccessively cleaned using the SC-1 solution for about 180 seconds.

When the cleaning process is accomplished, the critical dimension (CD)of the first contact hole 33 increases while the height of the firstinsulation layer pattern 32 decreases because the first insulation layerpattern 32 is somewhat etched.

When structures like bit lines (not shown) are formed under the firstinsulation layer patterns 32, portions of the structures may be exposedafter the cleaning process. Particularly, portions of the structures maybe seriously exposed near the sidewalls of the first contact holes 33.Thus, failures such as pattern bridges may occur in accordance with theexposure of the structures like the bit lines.

Considering the above-mentioned problem, spacers may be advantageouslyformed on the sidewall of the first contact holes 33 after the cleaningprocess. In this case, the spacer may be formed as follows.

A thin film for the spacers is continuously formed on the sidewalls andbottom faces of the first contact holes 33 and on the first insulationlayer patterns 32. For example, the thin film for the spacers includes asilicon nitride film or an oxide film. Though these films may beindependently formed to complete the thin film for the spacers, theoxide film and the silicon nitride film are alternatively formed insequence to complete the thin film for the spacers. Here, the oxide filmmay include middle temperature oxide (MTO).

The thin film is etched to remove portions of the thin film positionedon the first insulation layer patterns 32 and on the bottom faces of thefirst contact holes 33. Hence, the thin film remains only on thesidewalls of the first contact holes 33. The remaining portions of thethin film serve as the spacers.

Referring to FIG. 3B, a conductive film composed of a conductivematerial is deposited on the first insulation layer patterns 32 andfills the first contact holes 33. For example, the conductive materialincludes polysilicon.

In particular, the conductive film is formed on the first insulationlayer patterns 32 having the first contact holes 33 and fills the firstcontact holes 33. Portions of the conductive film positioned on thefirst insulation layer patterns 32 are removed. Here, the portions ofthe conductive film are preferably removed using a chemical mechanicalpolishing (CMP) process. In the CMP process, a polishing end point ispreferably set as the surfaces of the first insulation layer patterns32. That is, the conductive film is polished by the CMP process untilthe surfaces of the first insulation layer patterns 32 are exposed.Accordingly, the first contact holes 33 are filled up with theconductive material. When the first contact holes 33 are filled up withthe conductive material, contact plugs 34 for the bottom electrodes ofthe capacitors are formed.

Referring to FIG. 3C, a second insulation layer 36 and a thirdinsulation layer 38 are sequentially formed on the first insulationlayer patterns 32 and on the contact plugs 34. When the third insulationlayer 38 and the second insulation layer 36 are etched, the firstinsulation layer patterns 32 may be damaged due to the etchingselectivity between the first insulation layer patterns 32 and thesecond and third insulation layers 36 and 38

Therefore, an etch stop layer 35 is preferably formed on the firstinsulation layer patterns 32 and on the contact plugs 34. The etch stoplayer 35 prevents the first insulation layer patterns 32 from beingdamaged during the etching process for the third insulation layer 38 andthe second insulation layer 36. For example, the etch stop layer 35includes a silicon nitride film or an oxide film. Though these films maybe independently formed to complete the etch stop layer 35, the oxidefilm and the silicon nitride film are alternatively formed in sequenceto complete the etch stop layer 35. The oxide film may include middletemperature oxide (MTO).

When the etching selectivity of the second insulation layer 36 issmaller than that of the first insulation layer patterns 32, the firstinsulation layer patterns 32 near the upper portions of the contactholes 33 are somewhat etched. When the first insulation layer patterns32 near the upper portions of the contact holes 33 are etched, a patternbridge between adjacent contact holes 33 may form. If the pattern bridgeis generated, the electrical function of the capacitor may be damaged.

Therefore, the etching selectivity of the second insulation layer 36 ispreferably larger than that of the first insulation layer patterns 32.In other words, the etching selectivity of the second insulation layer36 is preferably higher than that of the first insulation layer patterns32. For example, the second insulation layer 36 is formed using BPSG.Here, the BPSG is preferably about 2.3 to 2.7% by weight of boron andabout 2.25 to 2.65% by weight of phosphorous.

As for the cylindrical shaped bottom electrode of the capacitor formedutilizing a third insulation layer pattern and a second insulation layerpattern, the critical dimension of a lower node is required to have avalue larger than that of an upper node in order to prevent the bottomelectrode from leaning or collapsing. When the third insulation layerpattern and the second insulation layer pattern are formed using by theetching process for the third insulation layer 38 and the secondinsulation layer 36, the critical dimension of a second contact holeformed through the second insulation layer pattern is required to have avalue larger than that of a third contact hole formed through the thirdinsulation layer pattern. For example, the third insulation layer 38includes an oxide film like a tetraethylorthosilicate (TEOS) film.

Referring to FIG. 3D, the third insulation layer 38 and the secondinsulation layer 36 are sequentially etched. The etching process isperformed by a photolithography process until the surfaces of thecontact plugs 34 are exposed. The second insulation layer 36 ispreferably etched to expose the etch stop layer 35. The sequentialetching process of the third insulation layer 38 and the secondinsulation layer 36 is performed by a wet etching process or a dryetching process. The wet etching process is preferably performed using aLAL solution. Here, the LAL solution preferably contains a fluorinecompound such as HF or NH₄F. In addition, the etching process for theetch stop layer 35 is preferably performed by a wet etching processusing a LAL solution or a phosphoric acid solution. When the etch stoplayer 35 includes an oxide film, the wet etching process using the LALsolution is advantageously performed. When the etch stop layer 35includes a silicon nitride film, the wet etching process is adequatelyperformed using the phosphoric acid solution. When the etch stop layer35 includes a composite film of silicon nitride and oxide, the wetetching process is performed sequentially using the phosphoric acidsolution and the LAL solution.

After these etching processes, the third insulation layer 38 and thesecond insulation layer 36 are respectively patterned into thirdinsulation layer patterns 38 a having third contact holes 38 b andsecond insulation layer patterns 36 a having second contact holes 36 b.Because the etching selectivity of the second insulation layer 36 isadjusted to have the value larger than that of the third insulationlayer 38, the critical dimension of the second contact hole 36 b formedthrough the second insulation layer pattern 36 a is larger than that ofthe third contact hole 38 b of the third insulation layer pattern 38 a.Additionally, the first insulation layer patterns 32 near the upperportions of the contact plugs 34 exposed during the etching process forthe second insulation layer 36 are hardly etched because the etchingselectivity of the second insulation layer 36 is adjusted to have thevalue larger than that of the first insulation layer patterns 32.

When the third insulation layer patterns 38 a and the second insulationlayer patterns 36 a are formed, contaminant particles are generated. Thecontaminants may remain on the third insulation layer patterns 38 a andon the second insulation layer patterns 38 b, thereby causing failuresin subsequent processes.

Therefore, a cleaning process for the third insulation layer patterns 38a and the second insulation layer patterns 36 a is preferably performed.The cleaning process is preferably a wet cleaning process that uses anSC-1 solution or an HF solution. Though the two solutions may beindependently used, it is preferable to sequentially use the HF solutionand then the SC-1 solution during the cleaning process. Here, thecleaning process using the SC-1 solution is performed at the temperatureof about 70° C. for about 7 minutes. Then, the cleaning process isperformed using the HF solution is performed at a temperature of about70° C. for about 160 seconds.

When the third insulation layer patterns 38 a and the second insulationlayer patterns 38 b are cleaned, the first insulation layer patterns 32may be damaged. Particularly, the first insulation layer patterns 32near the upper portions of the contact plugs 34 may be damaged.

Therefore, a protection layer (not shown) for protecting the damagedfirst insulation layer patterns 32 is preferably formed on the damagedportions of the first insulation layer patterns 32. For example, theprotection layer includes a silicon nitride film or an aluminum oxidefilm. Though the two films are independently formed to complete theprotection layer, a composite film including a silicon nitride film andan aluminum oxide film may be formed to complete the protection layer.In particular, the protection layer is formed as follows.

The protection layer is continuously formed on the third insulationlayer patterns 38 a, on the sidewalls of the third contact holes 38 b,and on the sidewalls and the bottom faces of the second contact holes 36b. Then, the protection layer on the third insulation layer patterns 38a is removed by a chemical mechanical polishing (CMP) process. As aresult, the protection layer remains on the sidewalls of the thirdcontact holes 38 b and on the sidewalls and the bottom faces of thesecond contact holes 36 b. Though the protection layer may be formed onthe damaged portions of the first insulation layer patterns 32 only, theprotection layer is preferably formed on the sidewalls of the thirdcontact holes 38 b and on the sidewalls and the bottom faces of thesecond contact holes 36 b.

The protection layer prevents the formation of a pattern bridge betweenadjacent contact plugs 34 caused by the damage of the first insulationlayer patterns 32 near the upper portions of the contact plugs 34.

A conductive film for the bottom electrodes of the capacitors iscontinuously formed on the sidewalls of the third contact holes 38 b andon the sidewalls and the bottom faces of the second contact holes 36 b.Particularly, the conductive film is continuously formed on the thirdinsulation layer patterns 38 a, on the sidewalls of the third contactholes 38 b, and on the sidewalls and the bottom faces of the secondcontact holes 36 b. Then, the conductive film on the third insulationlayer patterns 38 a is removed by a CMP process. As a result, theconductive film remains to form bottom electrodes 40. The bottomelectrodes 40 are formed on the sidewalls of the third contact holes 38b, and on the sidewalls and the bottom faces (adjacent to the contactplugs 34) of the second contact holes 36 b. Each of the bottomelectrodes 40 has an upper node 40 a and a lower node 40 b wherein thecritical dimension of the lower node 40 b is larger than that of theupper node 40 a because the critical dimension of the second contacthole 36 b is larger than that of the third contact hole 38 b.

FIG. 4 is an enlarged cross-sectional diagram illustrating the criticaldimension of the bottom electrode of the cylindrical shaped capacitorfabricated according to another embodiment of the invention.

Referring to FIG. 4, the critical dimension of the upper portion (CD41)of the upper node 40 a of the bottom electrode 40 is larger than that ofthe lower portion (CD42) of the upper node 40 a. In addition, thecritical dimension of the upper portion (CD43) of the lower node 40 b ofthe bottom electrode 40 is larger than that of a lower portion (CD44) ofthe lower node 40 b. Thus, the bottom electrode 40 has a geometricallystable structure.

The structures having the conductive film may be used as metal wiringsof a semiconductor device. In particular, an interlayer dielectric layeris formed on the structure having the conductive film after theconductive film is formed. Then, the interlayer dielectric layer isetched to form an interlayer dielectric layer pattern having a contacthole exposing the conductive film. Next, other films are additionallyformed on the resultant structure to be electrically connected to theconductive film. As described above, the conductive film may be used asthe metal wirings after performing a series of processes.

Referring now to FIG. 3E, the second insulation layer patterns 36 a andthe third insulation layer patterns 38 a are removed. Thus, cylindricalshaped bottom electrodes 40 of the capacitors are formed over thesubstrate 30. Here, the second insulation layer patterns 36 a and thethird insulation layer patterns 38 a are preferably removed by a wetetching process using a LAL solution.

When the protection layer is formed, the protection layer isadvantageously removed to complete the bottom electrode 40. In thiscase, the protection layer is preferably removed by a wet etchingprocess using a LAL solution or a phosphoric acid solution. When theprotection layer includes the aluminum oxide film, the wet etchingprocess using the LAL solution is performed to remove the protectionlayer. Meanwhile, the protection layer includes the silicon nitridefilm, the wet etching process using the phosphoric acid solution isexecuted to remove the protection layer.

In addition, the etch stop layer 35 remaining on the first insulationlayer patterns 32 is removed when the first insulation layer patterns 32are exposed according as the second insulation layer patterns 36 a andthe third insulation layer patterns 38 a are removed. In the case wherethe etch stop layer 35 includes a material substantially identical tothat of the protection layer, the etch stop layer 35 is simultaneouslyremoved along with the protection layer. Therefore, the etch stop layer35 is advantageously removed by the wet etching process using the LALsolution or the phosphoric acid solution.

According to an embodiment of the invention, the pattern bridge betweenthe contact plugs may be prevented by adjusting the etching selectivityof the insulation layer patterns formed on the upper portions of thecontact plugs. The likelihood of a pattern bridge is also reduced bypreventing the etching of the insulation layer patterns on the upperportions of the contact plugs. Although the insulation layer patterns onthe upper portions of the contact plugs are slightly damaged, theformation of the pattern bridge between the contact plugs can beefficiently prevented because the insulating protection layer is formedon the damaged insulation layer patterns. Therefore, the pattern bridgebetween contact plugs that is frequently caused during the formation ofthe cylindrical shaped capacitor can be effectively prevented.

Hereinafter, a method of forming a protection layer in accordance withanother embodiment of the invention will be described.

FIGS. 5 and 6 are cross-sectional diagrams illustrating a method offorming the bottom electrode of a cylindrical shaped capacitor having aprotection layer pattern according to another embodiment of theinvention.

Referring to FIG. 5, first insulation layer patterns 52 having firstcontact holes 53 are formed on a semiconductor substrate 50. Aconductive material is deposited on the first insulation layer patterns52 to fill up the first contact holes 53 so that contact plugs 54 forbottom electrodes of capacitors are formed in the first contact holes53.

Second insulation layer patterns 56 and third insulation layer patterns58 are successively formed on the first insulation layer patterns 52.The second insulation layer patterns 56 have second contact holes 56 aexposing the contact plugs 54 and the third insulation layer patterns 58have third contact holes 58 a. Alternatively, an etch stop layer 55 maybe additionally formed between the first insulation layer patterns 52and the second insulation layer patterns 56.

The first insulation layer patterns 52, the contact plugs 54, the secondinsulation layer patterns 56 and the third insulation layer patterns 58are formed by the processes identical to those described in FIGS. 3A to3D.

When the second insulation layer patterns 56 and the third insulationlayer patterns 58 are formed, the first insulation layer patterns 52near the upper portions of the contact plugs 54 may be damaged. If thefirst insulation layer patterns 52 are seriously impaired, patternbridges may generate between adjacent contact plugs 54. Thus, aprotection layer 59 is formed on the sidewalls of the third contactholes 58 a and on the sidewalls and bottom faces of the second contactholes 56 a. The protection layer 59 is formed as follows.

A thin film for the protection layer 59 is continuously formed on thethird insulation layer patterns 58, on the sidewalls of and the thirdcontact holes 58 a, and on the sidewalls and the bottom faces of thesecond contact holes 56 a. Next, the thin film on the third insulationlayer patterns 58 is removed by a CMP process to form the protectionlayer 59. Though the protection layer 59 may be formed on the damagedportions of the first insulation layer patterns 52 only, the protectionlayer 59 is preferably formed on the sidewalls of the third contactholes 58 a, and on the sidewalls and the bottom surfaces of the secondcontact holes 56 a.

When the first insulation layer patterns 52 are impaired, the protectionlayer 59 is formed on the impaired portions of the first insulationlayer patterns 52. For example, the protection layer 59 includes asilicon nitride film or an aluminum oxide film. Though these two filmsare independently utilized to form the protection layer 59, a compositefilm including a silicon nitride film and an aluminum oxide film may beemployed to form the protection layer 59.

A conductive film for the bottom electrodes 60 of capacitors is formedand processed to form the bottom electrodes 60 including lower nodes 60b and upper nodes 60 a. Here, the bottom electrodes 60 are formed inaccordance with the processes described in FIGS. 3D and 3E.

Referring to FIG. 6, after the second insulation layer patterns 56 andthe third insulation layer patterns 58 are removed, the protection layer59 and the etch stop layer 55 exposed according to the removal of thesecond and third insulation layer patterns 56 and 58 are removed. Thesecond insulation layer patterns 56, the third insulation layer patterns58, the protection layer 59, and the etch stop layer 55 are removed byprocesses substantially identical to those described in FIG. 3E. In thiscase, portions of the protection layer 59 remain on the first insulationlayer patterns 52 to form protection layer patterns 59 a covering thedamaged portions of the first insulation layer patterns 52. As a result,the bottom electrodes 60 having cylindrical shapes are formed over thesubstrate 50. Each of the bottom electrodes 60 includes the pad 51, thecontact plug 54, the protection layer pattern 59 a, the upper node 60 aand the lower 60 b. The upper and lower nodes 60 a and 60 b havecylindrical shapes. The upper node 60 a is connected to the lower node60 b. Here, the upper and lower nodes 60 a and 60 b are integrallyformed. Additionally, the critical dimension of the lower node 60 b ispreferably larger than that of the upper node 60 a. More specially, theprotection layer patterns 59 a are formed near the upper portions of thecontact plugs 54 of the bottom electrodes 60, thereby preventing thepattern bridge between the contact plugs 54 due to the protection layerpatterns 59 a. Therefore, the pattern bridge between contact plugs,which often occurs during the formation of the cylindrical shapedcapacitor, is prevented by the protection layer patterns 59 a.

Hereinafter, it will be described that a method of fabricating a DRAMdevice by employing the processes for forming the bottom electrode ofthe cylindrical shaped capacitor.

FIGS. 7A to 7D are cross-sectional diagrams illustrating a method offabricating a DRAM device according to still another embodiment of thepresent invention.

Referring to FIG. 7A, there is provided a substrate 70 having a trenchwherein an isolation layer 72 is formed. Gate electrodes Ga are formedin an active region of the substrate 70. Each of the gate electrodes Gaincludes a gate silicon oxide film pattern 74 a, a polysilicon filmpattern 74 b, and a tungsten silicide film pattern 74 c.

Lightly doped source/drain regions 80 are formed at portions of thesubstrate 70 exposed between the gate electrodes Ga by an ionimplantation process. Spacers 78 a are formed on the sidewalls of thegate electrode Ga, respectively. In addition, capping layer patterns 76are formed on top faces of the gate electrodes Ga, respectively. Heavilydoped source/drain regions are then formed at the exposed portions ofthe substrate 70 by an additional ion implantation process. As a result,gate electrodes Ga and lightly doped drain (LDD) source/drain regions 80are completed on the substrate 70. Here, the LDD source/drain regions 80correspond to contact regions such as capacitor contact regions and bitline contact regions.

Pads 82 are formed on the contact regions of the substrate 70 betweenthe gate electrodes Ga by filling a polysilicon film between the gateelectrodes Ga. Each of the pads 82 includes a first pad 82 a for thebottom electrode of a capacitor and a second pad 82 b for a bit line.Particularly, the polysilicon film is formed on the contact regions ofthe substrate 70 and on the gate electrodes Ga. A CMP process isperformed on the polysilicon film until the capping layer patterns 76 ofthe gate electrodes Ga are exposed. Portions of the polysilicon remainonly on the contact regions, thereby forming the pads 82 on the contactregions (that is, source/drain regions 80).

After a first interlayer dielectric layer 84 is formed on the resultingstructure, the first interlayer dielectric layer 84 is planarized by aCMP process or an etch-back process. Next, a bit line contact holeexposing the second pad 82 b for a bit line 88 is formed by aphotolithography process.

A conductive material is deposited to fill up the bit line contact holeso that a bit line contact plug 86 is formed in the bit line contacthole. The bit line 88 is formed on the first interlayer dielectric layer84 and is electrically connected to the bit line contact plug 86. Anoxidation preventing layer 90 is then formed on the bit line 88 toprevent the oxidation of the bit line 88 during subsequent processes.

Next, after a second interlayer dielectric layer 92 is formed on theoxidation preventing layer 90, the second interlayer dielectric layer 92is planarized by a CMP process. The second interlayer dielectric layer92 is planarized to have a thickness of about 500 Å. Because the secondinterlayer dielectric layer 92 has a relatively thin thickness of about500 Å, the bit line 88 may be damaged during subsequent processes.Therefore, a capping layer 94 having a thickness of about 2,000 Å isformed on the second interlayer dielectric layer 92 after theplanarization of the second interlayer dielectric layer 92. The cappinglayer 94 includes a BPSG film formed by a chemical vapor depositionprocess. In this case, the BPSG film contains about 4.0% by weight ofboron and about 3.5% by weight of phosphorous.

Referring to FIG. 7B, contact holes 96 are formed to expose the firstpads 82 a for the bottom electrode. The contact holes 96 are formed by adry etching process using a photoresist pattern as an etch mask.

A first wet cleaning process is performed for about 100 seconds using anHF solution diluted with water by a ratio of about 200:1. Then, a secondwet cleaning process is executed for about 180 seconds using an SC-1solution.

Spacers 98 are formed on the sidewalls of the contact holes 96. Inparticular, a middle temperature oxide (MTO) film and a silicon nitridefilm are continuously formed on the sidewalls and bottom faces of thecontact holes 96 and on the capping layer 94. Next, the MTO film and thesilicon nitride film on the bottom faces of the contact holes 96 and thecapping layer 94 are removed by an etching process, thereby forming thespacers 98 on the sidewalls of the contact holes 96.

Contact plugs 100 for the bottom electrode are formed in the contactholes 96 by filling the contact holes 96 using a conductive material. Asilicon oxide layer is formed on the contact plugs 100 and on thecapping layer 94 to a thickness of about 450 Å. The silicon oxide layerserves as an etch stop layer 102.

A molding layer 104 is formed on the etch stop layer 102. The moldinglayer 104 will be used to form the bottom electrodes having cylindricalshaped nodes by a molding process. The molding layer 104 includes a BPSGfilm 104 a and a plasma enhanced TEOS (PE-TEOS) film 104 b. The BPSGfilm 104 a contains about 2.50% by weight of boron and about 2.45% byweight of phosphorous. The molding layer 104 has an overall thickness ofabout 15,000 Å.

Referring to FIG. 7C, the molding layer 104 is etched to form moldinglayer patterns 106 including BPSG film patterns 106 a and PE-TEOS filmpatterns 106 b. Simultaneously, contact holes are formed through themolding layer patterns 106. The BPSG film patterns 106 a are positionedat lower portions of the contact holes while the PE-TEOS film patterns106 b are positioned at upper portions of the contact holes. Here, thecritical dimensions of the BPSG film patterns 106 a are larger thanthose of the PE-TEOS film patterns 106 b. That is, the lower portions ofthe contact holes are wider than the upper portions of the contactholes.

Because the capping layer 94 includes more boron and phosphorous thanthe BPSG film patterns 106 a of the molding layer patterns 106, theetching process for forming the molding layer pattern 106 may beinsufficiently performed.

After a primary wet cleaning process is performed on the resultantstructure at a temperature of about 70° C. using an HF solution dilutedwith water by ratio of about 200:1 for about 100 seconds, a secondarywet cleaning process is performed concerning the resultant structure ata temperature of about 70° C. using an SC-1 solution for about 180seconds.

After forming the molding layer patterns 106, a protection layer 108 isformed on the sidewalls of the contact holes that penetrate the moldinglayer patterns 106 to prevent the pattern bridge between contact plugs100. A conductive film for the bottom electrodes 110 is formed on thesurface of the protection layer 108 and on the bottom faces of thecontact holes.

Alternatively, the conductive film for the bottom electrodes 110 may beemployed as metal wirings. Namely, an interlayer dielectric layer isformed on the resultant structure having the conductive film for thebottom electrodes 110. Then, the interlayer dielectric layer ispatterned to form interlayer dielectric layer patterns having contactholes exposing the conductive film for the bottom electrodes 110. Anadditional conductive film is formed on the interlayer dielectric layerpatterns to electrically connect the conductive film for the bottomelectrodes 110, thereby utilizing the conductive film for the bottomelectrodes 110 as the metal wirings.

Referring to FIG. 7D, the molding layer patterns 106, the protectionlayer 108 and the etch stop layer 102 remaining on the capping layer 94are sequentially removed. Thus, the bottom electrodes 110 are formedover the substrate 70. Here, the bottom electrodes 110 include uppernodes 110 a and lower nodes 110 b, respectively. The nodes 110 a and 110b are electrically connected to the first pads 82 a through the contactplugs 100.

Thereafter, dielectric layers and top electrodes are formed on thebottom electrodes 110 to complete the capacitors having the cylindricalshapes. As a result, a DRAM cell is formed on the substrate 70, whichhas transistors including the gate electrodes Ga and the source/drainregion 80, a bit line for an electrical connection, and the capacitorhaving the cylindrical shapes.

According to an embodiment of the invention, the insulation layer nearthe upper portions of the contact plugs for the bottom electrodes is notcompletely etched, preventing the bridge between the contact plugs whenthe cylindrical shaped capacitors are formed. Although the insulationlayer near the upper portions of the contact plugs is etched somewhat,the bridge between the contact plugs may be prevented due to theremaining insulation layer near the upper portions of the contact plugs.

The method of the invention may be advantageously employed to form acylindrical shaped capacitor having a high height while simultaneouslypreventing the capacitor from collapsing.

Additionally, a semiconductor device including the capacitor hasimproved electrical reliability because bridges between the contactplugs caused by the etching of the upper portions of the contact plugsare prevented.

Furthermore, the structure having the conductive film for the nodes maybe sufficiently employed as metal wirings of a semiconductor device.

Embodiments of the invention will now be described in a non-limitingway.

In one aspect of the invention, a first insulation layer pattern havinga first etching rate and a first contact hole is formed on a substrate.A contact plug is formed in the contact hole, and a second insulationlayer having a second etching rate is formed on the first insulationlayer pattern and on the contact plug. The second insulation layer has asecond etching rate higher than the first etching rate. The secondinsulation layer is etched to form a second insulation layer patternhaving a second contact hole exposing the contact plug and a portion ofthe first insulation layer pattern near the contact plug. The etchingamount of portions of the first insulation layer pattern is reduced inaccordance with the etching rate difference between the second etchingrate and the first etching rate. A conductive film is continuouslyformed on the sidewall and on the bottom face of the second contacthole. The second insulation layer pattern is removed.

When the second insulation layer is etched, the etching rate of thefirst insulation layer pattern is adjusted to be smaller than that ofthe second insulation layer. Therefore, the first insulation layerpattern near the upper portion of the contact plug may not be etched tosome degree.

According to an embodiment of the invention, the bridge that is usuallygenerated during etching of the upper portion of the contact plug isprevented. A cylindrical shaped capacitor having a bottom electrode witha high height may be formed without danger of collapsing. As a result,the reliability of semiconductor devices that include the capacitor maybe improved.

In another aspect of the invention, a first insulation layer patternhaving a first contact hole is formed on a substrate. A contact plug fora bottom electrode of a capacitor is formed in the contact hole, and asecond insulation layer pattern is formed on the first insulation layerpattern. The second insulation layer pattern has a second contact holeexposing the contact plug. A protection layer is formed on a portion ofthe first insulation pattern exposed by the second contact hole and on asidewall of the second contact hole. A conductive film for the bottomelectrode is continuously formed on the protection layer and on thecontact plug. The second insulation layer pattern is removed, and theprotection layer is then partially removed.

According to another embodiment of the invention, the portion of thefirst insulation layer pattern near the upper portion of the contactplug may be slightly etched during the processes for forming thecapacitor. The protection layer formed near the first insulation layerpattern prevents the generation of a bridge between the contact plugs.Therefore, the capacitor has a cylindrical shape wherein the height ofthe capacitor is augmented without danger of collapse. As a result, thereliability of a semiconductor device including the capacitor can beenhanced.

In still another aspect of the invention, a bottom electrode of acapacitor includes a contact plug formed on a substrate, a node formedon the upper portion of the contact plug, and a protection layer patternformed near the contact plug. The contact plug is electrically connectedto the node, and the protection layer pattern prevents the electricalconnection between the contact plug and an adjacent contact plug.

According to still another embodiment of the invention, the bottomelectrode includes the protection layer pattern to prevent the formationof a bridge between adjacent contact plugs. When the bottom electrodehaving the protection layer pattern is employed for the capacitor havinga cylindrical shape, the capacitor can have improved electriccharacteristics as well as stable structure.

Exemplary embodiments of the invention have been disclosed herein and,although specific terms are employed, they are used and are to beinterpreted in a generic and descriptive sense only and not for purposeof limitation. Accordingly, it will be understood by those of ordinaryskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

1. A bottom electrode of a capacitor of a semiconductor devicecomprising: a contact plug formed on a substrate; a node formed on thecontact plug; and a protection layer pattern formed near the contactplug, wherein the contact plug is electrically connected to the node,and the protection layer pattern prevents an electrical connectionbetween the contact plug and an adjacent contact plug.
 2. The bottomelectrode of claim 1, wherein the protection layer pattern comprises afilm chosen from the group consisting of a silicon nitride film, analuminum oxide film, and a composite film that includes a siliconnitride film and an aluminum oxide film.
 3. The bottom electrode ofclaim 1, wherein the node has a cylindrical shape.
 4. The bottomelectrode of claim 1, wherein the node comprises an upper node and alower node, and wherein a critical dimension of the lower node is largerthan a critical dimension of the upper node.